Compare text

Find the difference between two text files

Real-time diff
Unified diff
Collapse lines
Highlight change
Syntax highlighting
Tools
Diffchecker Desktop icon
Diffchecker Desktop The most secure way to run Diffchecker. Get the Diffchecker Desktop app: your diffs never leave your computer!Get Desktop

Comparing sensitive data, confidential files or internal emails?

Most legal and privacy policies prohibit uploading sensitive data online. Diffchecker Desktop ensures your confidential information never leaves your computer. Work offline and compare documents securely.

Download Diffchecker DesktopLearn more

Untitled diff

Created Diff never expires
24 removals
76 lines
40 additions
91 lines
+/* Exynos USB PHY registers */
+/* Exynos USB PHY registers */
+
+
+/* PHY power control */
+/* PHY power control */
+#define EXYNOS_421x_UPHYPWR 0x0
+#define EXYNOS_421x_UPHYPWR 0x0
+
+
+#define EXYNOS_421x_UPHYPWR_DEV_SUSPEND (1 << 0)
+#define EXYNOS_421x_UPHYPWR_DEV_SUSPEND (1 << 0)
+#define EXYNOS_421x_UPHYPWR_DEV_PWR (1 << 3)
+#define EXYNOS_421x_UPHYPWR_DEV_PWR (1 << 3)
+#define EXYNOS_421x_UPHYPWR_DEV_OTG_PWR (1 << 4)
+#define EXYNOS_421x_UPHYPWR_DEV_OTG_PWR (1 << 4)
+#define EXYNOS_421x_UPHYPWR_DEV_SLEEP (1 << 5)
+#define EXYNOS_421x_UPHYPWR_DEV_SLEEP (1 << 5)
+#define EXYNOS_421x_UPHYPWR_DEV ( \
+#define EXYNOS_421x_UPHYPWR_DEV ( \
+ EXYNOS_421x_UPHYPWR_DEV_SUSPEND | \
+ EXYNOS_421x_UPHYPWR_DEV_SUSPEND | \
+ EXYNOS_421x_UPHYPWR_DEV_PWR | \
+ EXYNOS_421x_UPHYPWR_DEV_PWR | \
+ EXYNOS_421x_UPHYPWR_DEV_OTG_PWR | \
+ EXYNOS_421x_UPHYPWR_DEV_OTG_PWR | \
+ EXYNOS_421x_UPHYPWR_DEV_SLEEP)
+ EXYNOS_421x_UPHYPWR_DEV_SLEEP)
+
+
+#define EXYNOS_421x_UPHYPWR_HOST_SUSPEND (1 << 6)
+#define EXYNOS_421x_UPHYPWR_HOST_SUSPEND (1 << 6)
+#define EXYNOS_421x_UPHYPWR_HOST_PWR (1 << 7)
+#define EXYNOS_421x_UPHYPWR_HOST_PWR (1 << 7)
+#define EXYNOS_421x_UPHYPWR_HOST_SLEEP (1 << 8)
+#define EXYNOS_421x_UPHYPWR_HOST_SLEEP (1 << 8)
+#define EXYNOS_421x_UPHYPWR_HOST ( \
+#define EXYNOS_421x_UPHYPWR_HOST ( \
+ EXYNOS_421x_UPHYPWR_HOST_SUSPEND | \
+ EXYNOS_421x_UPHYPWR_HOST_SUSPEND | \
+ EXYNOS_421x_UPHYPWR_HOST_PWR | \
+ EXYNOS_421x_UPHYPWR_HOST_PWR | \
+ EXYNOS_421x_UPHYPWR_HOST_SLEEP)
+ EXYNOS_421x_UPHYPWR_HOST_SLEEP)
+
+
+#define EXYNOS_421x_UPHYPWR_HSCI0_SUSPEND (1 << 9)
+#define EXYNOS_421x_UPHYPWR_HSCI0_SUSPEND (1 << 9)
+#define EXYNOS_421x_UPHYPWR_HSCI0_SLEEP (1 << 10)
+#define EXYNOS_421x_UPHYPWR_HSCI0_PWR (1 << 10)
+#define EXYNOS_421x_UPHYPWR_HSCI0_SLEEP (1 << 11)
+#define EXYNOS_421x_UPHYPWR_HSCI0 ( \
+#define EXYNOS_421x_UPHYPWR_HSCI0 ( \
+ EXYNOS_421x_UPHYPWR_HSCI0_SUSPEND | \
+ EXYNOS_421x_UPHYPWR_HSCI0_SUSPEND | \
+ EXYNOS_421x_UPHYPWR_HSCI0_PWR | \
+ EXYNOS_421x_UPHYPWR_HSCI0_SLEEP)
+ EXYNOS_421x_UPHYPWR_HSCI0_SLEEP)
+
+
+#define EXYNOS_421x_UPHYPWR_HSCI1_SUSPEND (1 << 11)
+#define EXYNOS_421x_UPHYPWR_HSCI1_SUSPEND (1 << 12)
+#define EXYNOS_421x_UPHYPWR_HSCI1_SLEEP (1 << 12)
+#define EXYNOS_421x_UPHYPWR_HSCI1_PWR (1 << 13)
+#define EXYNOS_421x_UPHYPWR_HSCI1_SLEEP (1 << 14)
+#define EXYNOS_421x_UPHYPWR_HSCI1 ( \
+#define EXYNOS_421x_UPHYPWR_HSCI1 ( \
+ EXYNOS_421x_UPHYPWR_HSCI1_SUSPEND | \
+ EXYNOS_421x_UPHYPWR_HSCI1_SUSPEND | \
+ EXYNOS_421x_UPHYPWR_HSCI1_PWR | \
+ EXYNOS_421x_UPHYPWR_HSCI1_SLEEP)
+ EXYNOS_421x_UPHYPWR_HSCI1_SLEEP)
+
+
+/* PHY clock control */
+/* PHY clock control */
+#define EXYNOS_421x_UPHYCLK 0x4
+#define EXYNOS_421x_UPHYCLK 0x4
+
+
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_MASK (0x3 << 0)
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_MASK (0x7 << 0)
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0)
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_9MHZ6 (0x0 << 0)
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0)
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_10MHZ (0x1 << 0)
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_19MHZ2 (0x3 << 0)
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_20MHZ (0x4 << 0)
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_24MHZ (0x5 << 0)
+#define EXYNOS_421x_UPHYCLK_PHYFSEL_50MHZ (0x7 << 0)
+
+
+#define EXYNOS_421x_UPHYCLK_PHY0_ID_PULLUP (0x1 << 2)
+#define EXYNOS_421x_UPHYCLK_PHY0_ID_PULLUP (0x1 << 3)
+#define EXYNOS_421x_UPHYCLK_PHY0_COMMON_ON (0x1 << 4)
+#define EXYNOS_421x_UPHYCLK_PHY0_COMMON_ON (0x1 << 4)
+#define EXYNOS_421x_UPHYCLK_PHY1_COMMON_ON (0x1 << 7)
+#define EXYNOS_421x_UPHYCLK_PHY1_COMMON_ON (0x1 << 7)
+
+
+#define EXYNOS_421x_UPHYCLK_HSIC_REFCLK_MASK (0x7f << 10)
+#define EXYNOS_421x_UPHYCLK_HSIC_REFCLK_12MHZ (0x24 << 10)
+#define EXYNOS_421x_UPHYCLK_HSIC_REFCLK_15MHZ (0x1c << 10)
+#define EXYNOS_421x_UPHYCLK_HSIC_REFCLK_16MHZ (0x1a << 10)
+#define EXYNOS_421x_UPHYCLK_HSIC_REFCLK_19MHZ2 (0x15 << 10)
+#define EXYNOS_421x_UPHYCLK_HSIC_REFCLK_20MHZ (0x14 << 10)
+
+/* PHY reset control */
+/* PHY reset control */
+#define EXYNOS_421x_UPHYRST 0x8
+#define EXYNOS_421x_UPHYRST 0x8
+
+
+#define EXYNOS_421x_URSTCON_DEVICE (1 << 0)
+#define EXYNOS_421x_URSTCON_DEVICE (1 << 0)
+#define EXYNOS_421x_URSTCON_OTG_HLINK (1 << 1)
+#define EXYNOS_421x_URSTCON_OTG_HLINK (1 << 1)
+#define EXYNOS_421x_URSTCON_OTG_PHYLINK (1 << 2)
+#define EXYNOS_421x_URSTCON_OTG_PHYLINK (1 << 2)
+#define EXYNOS_421x_URSTCON_PHY1_ALL (1 << 3)
+#define EXYNOS_421x_URSTCON_HOST_PHY (1 << 3)
+#define EXYNOS_421x_URSTCON_PHY1_P0 (1 << 4)
+#define EXYNOS_421x_URSTCON_PHY1 (1 << 4)
+#define EXYNOS_421x_URSTCON_PHY1_P1P2 (1 << 5)
+#define EXYNOS_421x_URSTCON_HSIC0 (1 << 5)
+#define EXYNOS_421x_URSTCON_HOST_LINK_ALL (1 << 6)
+#define EXYNOS_421x_URSTCON_HSIC1 (1 << 6)
+#define EXYNOS_421x_URSTCON_HOST_LINK_P0 (1 << 7)
+#define EXYNOS_421x_URSTCON_HOST_LINK_ALL (1 << 7)
+#define EXYNOS_421x_URSTCON_HOST_LINK_P1 (1 << 8)
+#define EXYNOS_421x_URSTCON_HOST_LINK_P0 (1 << 8)
+#define EXYNOS_421x_URSTCON_HOST_LINK_P2 (1 << 9)
+#define EXYNOS_421x_URSTCON_HOST_LINK_P1 (1 << 9)
+#define EXYNOS_421x_URSTCON_HOST_LINK_P2 (1 << 10)
+
+
+/* Isolation, configured in the power management unit */
+/* Isolation, configured in the power management unit */
+#define EXYNOS_421x_USB_ISOL_DEVICE_OFFSET 0x704
+#define EXYNOS_421x_USB_ISOL_OFFSET 0x704
+#define EXYNOS_421x_USB_ISOL_DEVICE (1 << 0)
+#define EXYNOS_421x_USB_ISOL_OTG (1 << 0)
+#define EXYNOS_421x_USB_ISOL_HOST_OFFSET 0x708
+#define EXYNOS_421x_USB_ISOL_HSIC0_OFFSET 0x708
+#define EXYNOS_421x_USB_ISOL_HOST (1 << 0)
+#define EXYNOS_421x_USB_ISOL_HSIC0 (1 << 0)
+
+#define EXYNOS_421x_USB_ISOL_HSIC1_OFFSET 0x70c
+/* USBYPHY1 Floating prevention */
+#define EXYNOS_421x_USB_ISOL_HSIC1 (1 << 0)
+#define EXYNOS_421x_UPHY1CON 0x34
+#define EXYNOS_421x_UPHY1CON_FLOAT_PREVENTION 0x1
+
+
+/* Mode switching SUB Device <-> Host */
+/* Mode switching SUB Device <-> Host */
+#define EXYNOS_421x_MODE_SWITCH_OFFSET 0x21c
+#define EXYNOS_421x_MODE_SWITCH_OFFSET 0x21c
+#define EXYNOS_421x_MODE_SWITCH_MASK 1
+#define EXYNOS_421x_MODE_SWITCH_MASK 1
+#define EXYNOS_421x_MODE_SWITCH_DEVICE 0
+#define EXYNOS_421x_MODE_SWITCH_DEVICE 0
+#define EXYNOS_421x_MODE_SWITCH_HOST 1
+#define EXYNOS_421x_MODE_SWITCH_HOST 1
+
Saved diffs