round robin arbiter dlatch synthesis error
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// Credit: https://github.com/thomasrussellmurphy/stx_cookbook/blob/master/arbitration/arbiter.v
// Credit: https://github.com/thomasrussellmurphy/stx_cookbook/blob/master/arbitration/arbiter.v
// Copyright 2007 Altera Corporation. All rights reserved.
// Copyright 2007 Altera Corporation. All rights reserved.
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// Altera products are protected under numerous U.S. and foreign patents,
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// maskwork rights, copyrights and other intellectual property laws.
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//
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/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// baeckler - 02-13-2007
// baeckler - 02-13-2007
//
//
// 'base' is a one hot signal indicating the first request
// 'base' is a one hot signal indicating the first request
// that should be considered for a grant. Followed by higher
// that should be considered for a grant. Followed by higher
// indexed requests, then wrapping around.
// indexed requests, then wrapping around.
//
//
// https://www.reddit.com/r/FPGA/comments/axutbt/understanding_a_simple_roundrobin_arbiter_verilog/
// https://www.reddit.com/r/FPGA/comments/axutbt/understanding_a_simple_roundrobin_arbiter_verilog/
module arbiter #(parameter WIDTH = 16) (clk, reset, req, grant);
module arbiter #(parameter WIDTH = 16) (clk, reset, req, grant);
input clk, reset;
input clk, reset;
input [WIDTH-1:0] req;
input [WIDTH-1:0] req;
output reg [WIDTH-1:0] grant;
output reg [WIDTH-1:0] grant;
// note that 'base' is one-hot vector,
// note that 'base' is one-hot vector,
// 'base' signal helps round-robin arbiter to decide which 'req' to start servicing
// 'base' signal helps round-robin arbiter to decide which 'req' to start servicing
reg [WIDTH-1:0] base;
reg [WIDTH-1:0] base;
wire [2*WIDTH-1:0] double_req = {req,req};
wire [2*WIDTH-1:0] double_req = {req,req};
wire [2*WIDTH-1:0] double_grant = double_req & ~(double_req-base);
wire [2*WIDTH-1:0] double_grant = double_req & ~(double_req-base);
always @(*)
always @(*)
begin
begin
if(reset) grant = 0;
if(reset) grant = 0;
else grant = double_grant[WIDTH-1:0] | double_grant[2*WIDTH-1:WIDTH];
else grant = double_grant[WIDTH-1:0] | double_grant[2*WIDTH-1:WIDTH];
end
end
wire [$clog2(WIDTH)-1:0] granted_index;
wire [$clog2(WIDTH)-1:0] granted_index;
// for one-hot encoding to binary encoding conversion
// for one-hot encoding to binary encoding conversion
oh_to_idx #(WIDTH) port_index (.one_hot(grant), .index(granted_index));
oh_to_idx #(WIDTH) port_index (.one_hot(grant), .index(granted_index));
reg first_clock_passed;
reg first_clock_passed;
always @(posedge clk) first_clock_passed <= 1;
always @(posedge clk) first_clock_passed <= 1;
always @(posedge clk)
always @(*)
begin
begin
// starts round-robin arbiter with req #0 getting prioritized first
// starts round-robin arbiter with req #0 getting prioritized first
if(reset || first_clock_passed) base = 1;
if(reset || first_clock_passed) base = 1;
// 'base' is a one-hot signal which rotates
// 'base' is a one-hot signal which rotates
// after the corresponding 'req' had been serviced)
// after the corresponding 'req' had been serviced)
// Rotation wraps around upon reaching MSB
// Rotation wraps around upon reaching MSB
else if(req[granted_index] == 0)
else if(req[granted_index] == 0)
base = (base[WIDTH-1]) ? 1 : (base << 1);
base = (base[WIDTH-1]) ? 1 : (base << 1);
end
end
endmodule
endmodule