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; Assembly listing for method helloworld.loop:PartitionScalar(byref,byref,byref,int):ulong (
FullOpts
)
; Assembly listing for method helloworld.loop:PartitionScalar(byref,byref,byref,int):ulong (
Tier1
)
; Emitting BLENDED_CODE for generic ARM64 - Windows
; Emitting BLENDED_CODE for generic ARM64 - Windows
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;
FullOpts
code
;
Tier1
code
; optimized code
; optimized code
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; optimized using Dynamic PGO
; fp based frame
; fp based frame
; fully interruptible
; fully interruptible
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;
No
PGO
data
;
with Dynamic
PGO
: fgCalledCount is 717568
; invoked as altjit
; invoked as altjit
; Final local variable assignments
; Final local variable assignments
;
;
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; V00 arg0 [V00,T0
3
] ( 4,
7
) byref -> x0 single-def
; V00 arg0 [V00,T0
4
] ( 4,
14.04
) byref -> x0 single-def
; V01 arg1 [V01,T0
6
] ( 3,
4
) byref -> x1 single-def
; V01 arg1 [V01,T0
8
] ( 3,
2.21
) byref -> x1 single-def
; V02 arg2 [V02,T0
7
] ( 3,
4
) byref -> x2 single-def
; V02 arg2 [V02,T0
5
] ( 3,
12.82
) byref -> x2 single-def
; V03 arg3 [V03,T0
8
] ( 3, 3
) int -> x3 single-def
; V03 arg3 [V03,T0
7
] ( 3, 3
.00
) int -> x3 single-def
;* V04 loc0 [V04,T11] ( 0, 0 ) long -> zero-ref
;* V04 loc0 [V04,T11] ( 0, 0 ) long -> zero-ref
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; V05 loc1 [V05,T
05
] ( 4,
7
) long -> x4
; V05 loc1 [V05,T
10
] ( 4,
1.64
) long -> x4
; V06 loc2 [V06,T0
4
] ( 5,
8
) long -> x5
; V06 loc2 [V06,T0
0
] ( 5,
34.47
) long -> x5
; V07 loc3 [V07,T0
9
] ( 2,
5
) int -> x6 single-def
; V07 loc3 [V07,T0
6
] ( 2,
12.04
) int -> x6 single-def
;# V08 OutArgs [V08 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;# V08 OutArgs [V08 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
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; V09 cse0 [V09,T0
2
] ( 4,
12
) int -> x8 "CSE #03: aggressive"
; V09 cse0 [V09,T0
3
] ( 4,
33.11
) int -> x8 "CSE #03: aggressive"
; V10 cse1 [V10,T
10
] ( 3, 2.
25
) long -> x3 "CSE #01: aggressive"
; V10 cse1 [V10,T
09
] ( 3, 2.
92
) long -> x3 "CSE #01: aggressive"
; V11 rat0 [V11,T0
0
] ( 4,
12.25
) long -> x7 "Strength reduced derived IV"
; V11 rat0 [V11,T0
1
] ( 4,
34.03
) long -> x7 "Strength reduced derived IV"
; V12 rat1 [V12,T0
1
] ( 4,
12.25
) long -> x3 "Trip count IV"
; V12 rat1 [V12,T0
2
] ( 4,
34.03
) long -> x3 "Trip count IV"
;
;
; Lcl frame size = 0
; Lcl frame size = 0
G_M47887_IG01: ;; offset=0x0000
G_M47887_IG01: ;; offset=0x0000
stp fp, lr, [sp, #-0x10]!
stp fp, lr, [sp, #-0x10]!
mov fp, sp
mov fp, sp
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;; size=8 bbWeight=1
PerfScore 1.50
;; size=8 bbWeight=1
.00
PerfScore 1.50
G_M47887_IG02: ;; offset=0x0008
G_M47887_IG02: ;; offset=0x0008
mov x4, xzr
mov x4, xzr
mov x5, xzr
mov x5, xzr
ldr x6, [x0]
ldr x6, [x0]
ldr w6, [x6]
ldr w6, [x6]
sxtw x3, w3
sxtw x3, w3
cmp x3, #0
cmp x3, #0
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ble G_M47887_IG0
8
ble G_M47887_IG0
7
;; size=28 bbWeight=1
PerfScore 9.00
;; size=28 bbWeight=1
.00
PerfScore 9.00
G_M47887_IG03: ;; offset=0x0024
G_M47887_IG03: ;; offset=0x0024
mov x7, xzr
mov x7, xzr
align [0 bytes for IG04]
align [0 bytes for IG04]
align [0 bytes]
align [0 bytes]
align [0 bytes]
align [0 bytes]
align [0 bytes]
align [0 bytes]
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;; size=4 bbWeight=0.
25
PerfScore 0.
12
;; size=4 bbWeight=0.
92
PerfScore 0.
46
G_M47887_IG04: ;; offset=0x0028
G_M47887_IG04: ;; offset=0x0028
ldr x8, [x0]
ldr x8, [x0]
ldr w8, [x8, x7]
ldr w8, [x8, x7]
cmp w8, w6
cmp w8, w6
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blo G_M47887_IG0
6
blo G_M47887_IG0
9
;; size=16 bbWeight=
4 PerfScore
30.00
;; size=16 bbWeight=
11.0
4 PerfScore
82.78
G_M47887_IG05: ;; offset=0x0038
G_M47887_IG05: ;; offset=0x0038
ldr x9, [x2]
ldr x9, [x2]
str w8, [x9, x5, LSL #2]
str w8, [x9, x5, LSL #2]
add x5, x5, #1
add x5, x5, #1
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b G_M47887_IG07
;; size=
12
bbWeight=
10.8
2 PerfScore
48.71
Text moved with changes to lines 70-74 (97.1% similarity)
;; size=
16
bbWeight=
2 PerfScore
11.00
G_M47887_IG06: ;; offset=
0x0044
G_M47887_IG06: ;; offset=
0x0048
ldr x9, [x1]
str w8, [x9, x4, LSL #2]
add x4, x4, #1
;; size=12 bbWeight=2 PerfScore 9.00
G_M47887_IG07: ;; offset=0x0054
add x7, x7, #4
add x7, x7, #4
sub x3, x3, #1
sub x3, x3, #1
cbnz x3, G_M47887_IG04
cbnz x3, G_M47887_IG04
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;; size=12 bbWeight=
4 PerfScore
8.00
;; size=12 bbWeight=
11.0
4 PerfScore
22.07
G_M47887_IG0
8
: ;; offset=0x00
6
0
G_M47887_IG0
7
: ;; offset=0x00
5
0
mov x0, x5
mov x0, x5
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;; size=4 bbWeight=1
PerfScore 0.50
;; size=4 bbWeight=1
.00
PerfScore 0.50
G_M47887_IG0
9
: ;; offset=0x00
6
4
G_M47887_IG0
8
: ;; offset=0x00
5
4
ldp fp, lr, [sp], #0x10
ldp fp, lr, [sp], #0x10
ret lr
ret lr
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Text moved with changes from lines 58-62 (97.1% similarity)
;; size=8 bbWeight=1
PerfScore 2.00
;; size=8 bbWeight=1
.00
PerfScore 2.00
G_M47887_IG09: ;; offset=0x005C
ldr x9, [x1]
str w8, [x9, x4, LSL #2]
add x4, x4, #1
b G_M47887_IG06
;; size=16 bbWeight=0.21 PerfScore 1.17
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; Total bytes of code 108, prolog size 8, PerfScore
71.12
, instruction count 31, allocated bytes for code 108 (MethodHash=e74944f0) for method helloworld.loop:PartitionScalar(byref,byref,byref,int):ulong (
FullOpts
)
; Total bytes of code 108, prolog size 8, PerfScore
168.19
, instruction count 31, allocated bytes for code 108 (MethodHash=e74944f0) for method helloworld.loop:PartitionScalar(byref,byref,byref,int):ulong (
Tier1
)
; ============================================================
; ============================================================
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; Assembly listing for method helloworld.loop:PartitionScalar(byref,byref,byref,int):ulong (FullOpts) ; Emitting BLENDED_CODE for generic ARM64 - Windows ; FullOpts code ; optimized code ; fp based frame ; fully interruptible ; No PGO data ; invoked as altjit ; Final local variable assignments ; ; V00 arg0 [V00,T03] ( 4, 7 ) byref -> x0 single-def ; V01 arg1 [V01,T06] ( 3, 4 ) byref -> x1 single-def ; V02 arg2 [V02,T07] ( 3, 4 ) byref -> x2 single-def ; V03 arg3 [V03,T08] ( 3, 3 ) int -> x3 single-def ;* V04 loc0 [V04,T11] ( 0, 0 ) long -> zero-ref ; V05 loc1 [V05,T05] ( 4, 7 ) long -> x4 ; V06 loc2 [V06,T04] ( 5, 8 ) long -> x5 ; V07 loc3 [V07,T09] ( 2, 5 ) int -> x6 single-def ;# V08 OutArgs [V08 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V09 cse0 [V09,T02] ( 4, 12 ) int -> x8 "CSE #03: aggressive" ; V10 cse1 [V10,T10] ( 3, 2.25) long -> x3 "CSE #01: aggressive" ; V11 rat0 [V11,T00] ( 4, 12.25) long -> x7 "Strength reduced derived IV" ; V12 rat1 [V12,T01] ( 4, 12.25) long -> x3 "Trip count IV" ; ; Lcl frame size = 0 G_M47887_IG01: ;; offset=0x0000 stp fp, lr, [sp, #-0x10]! mov fp, sp ;; size=8 bbWeight=1 PerfScore 1.50 G_M47887_IG02: ;; offset=0x0008 mov x4, xzr mov x5, xzr ldr x6, [x0] ldr w6, [x6] sxtw x3, w3 cmp x3, #0 ble G_M47887_IG08 ;; size=28 bbWeight=1 PerfScore 9.00 G_M47887_IG03: ;; offset=0x0024 mov x7, xzr align [0 bytes for IG04] align [0 bytes] align [0 bytes] align [0 bytes] ;; size=4 bbWeight=0.25 PerfScore 0.12 G_M47887_IG04: ;; offset=0x0028 ldr x8, [x0] ldr w8, [x8, x7] cmp w8, w6 blo G_M47887_IG06 ;; size=16 bbWeight=4 PerfScore 30.00 G_M47887_IG05: ;; offset=0x0038 ldr x9, [x2] str w8, [x9, x5, LSL #2] add x5, x5, #1 b G_M47887_IG07 ;; size=16 bbWeight=2 PerfScore 11.00 G_M47887_IG06: ;; offset=0x0048 ldr x9, [x1] str w8, [x9, x4, LSL #2] add x4, x4, #1 ;; size=12 bbWeight=2 PerfScore 9.00 G_M47887_IG07: ;; offset=0x0054 add x7, x7, #4 sub x3, x3, #1 cbnz x3, G_M47887_IG04 ;; size=12 bbWeight=4 PerfScore 8.00 G_M47887_IG08: ;; offset=0x0060 mov x0, x5 ;; size=4 bbWeight=1 PerfScore 0.50 G_M47887_IG09: ;; offset=0x0064 ldp fp, lr, [sp], #0x10 ret lr ;; size=8 bbWeight=1 PerfScore 2.00 ; Total bytes of code 108, prolog size 8, PerfScore 71.12, instruction count 31, allocated bytes for code 108 (MethodHash=e74944f0) for method helloworld.loop:PartitionScalar(byref,byref,byref,int):ulong (FullOpts) ; ============================================================
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; Assembly listing for method helloworld.loop:PartitionScalar(byref,byref,byref,int):ulong (Tier1) ; Emitting BLENDED_CODE for generic ARM64 - Windows ; Tier1 code ; optimized code ; optimized using Dynamic PGO ; fp based frame ; fully interruptible ; with Dynamic PGO: fgCalledCount is 717568 ; invoked as altjit ; Final local variable assignments ; ; V00 arg0 [V00,T04] ( 4, 14.04) byref -> x0 single-def ; V01 arg1 [V01,T08] ( 3, 2.21) byref -> x1 single-def ; V02 arg2 [V02,T05] ( 3, 12.82) byref -> x2 single-def ; V03 arg3 [V03,T07] ( 3, 3.00) int -> x3 single-def ;* V04 loc0 [V04,T11] ( 0, 0 ) long -> zero-ref ; V05 loc1 [V05,T10] ( 4, 1.64) long -> x4 ; V06 loc2 [V06,T00] ( 5, 34.47) long -> x5 ; V07 loc3 [V07,T06] ( 2, 12.04) int -> x6 single-def ;# V08 OutArgs [V08 ] ( 1, 1 ) struct ( 0) [sp+0x00] do-not-enreg[XS] addr-exposed "OutgoingArgSpace" ; V09 cse0 [V09,T03] ( 4, 33.11) int -> x8 "CSE #03: aggressive" ; V10 cse1 [V10,T09] ( 3, 2.92) long -> x3 "CSE #01: aggressive" ; V11 rat0 [V11,T01] ( 4, 34.03) long -> x7 "Strength reduced derived IV" ; V12 rat1 [V12,T02] ( 4, 34.03) long -> x3 "Trip count IV" ; ; Lcl frame size = 0 G_M47887_IG01: ;; offset=0x0000 stp fp, lr, [sp, #-0x10]! mov fp, sp ;; size=8 bbWeight=1.00 PerfScore 1.50 G_M47887_IG02: ;; offset=0x0008 mov x4, xzr mov x5, xzr ldr x6, [x0] ldr w6, [x6] sxtw x3, w3 cmp x3, #0 ble G_M47887_IG07 ;; size=28 bbWeight=1.00 PerfScore 9.00 G_M47887_IG03: ;; offset=0x0024 mov x7, xzr align [0 bytes for IG04] align [0 bytes] align [0 bytes] align [0 bytes] ;; size=4 bbWeight=0.92 PerfScore 0.46 G_M47887_IG04: ;; offset=0x0028 ldr x8, [x0] ldr w8, [x8, x7] cmp w8, w6 blo G_M47887_IG09 ;; size=16 bbWeight=11.04 PerfScore 82.78 G_M47887_IG05: ;; offset=0x0038 ldr x9, [x2] str w8, [x9, x5, LSL #2] add x5, x5, #1 ;; size=12 bbWeight=10.82 PerfScore 48.71 G_M47887_IG06: ;; offset=0x0044 add x7, x7, #4 sub x3, x3, #1 cbnz x3, G_M47887_IG04 ;; size=12 bbWeight=11.04 PerfScore 22.07 G_M47887_IG07: ;; offset=0x0050 mov x0, x5 ;; size=4 bbWeight=1.00 PerfScore 0.50 G_M47887_IG08: ;; offset=0x0054 ldp fp, lr, [sp], #0x10 ret lr ;; size=8 bbWeight=1.00 PerfScore 2.00 G_M47887_IG09: ;; offset=0x005C ldr x9, [x1] str w8, [x9, x4, LSL #2] add x4, x4, #1 b G_M47887_IG06 ;; size=16 bbWeight=0.21 PerfScore 1.17 ; Total bytes of code 108, prolog size 8, PerfScore 168.19, instruction count 31, allocated bytes for code 108 (MethodHash=e74944f0) for method helloworld.loop:PartitionScalar(byref,byref,byref,int):ulong (Tier1) ; ============================================================
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